This invention relates generally to the field of data processing systems and more specifically to a method and system for data transfer.
The increasing complexity and use of data processing systems has resulted in the demand for faster and more efficient methods of data transfer. Data transfer operations that require processing of the data by a processing unit, however, may slow down or decrease the efficiency of the data processing system. Accordingly, eliminating the need for intervention by the primary processor system is an effective approach for improving the speed and efficiency of data transfer. A direct memory access unit (DMA) may be used to transfer data to and from a memory without the intervention of a primary processing unit. To transfer data from a first memory through a transfer memory to a second memory, a first DMA reads the data from the first memory and then writes the data to the transfer memory. Then, a second DMA reads the data from the transfer memory and then writes the data to the second memory, thus completing the data transfer without processor intervention. Known methods and systems of data transfer using DMAs, however, have not been completely satisfactory with respect to speed and efficiency.
A known method of data transfer uses a transfer memory with an X-Y buffer system. To transfer data from the first DMA through the transfer memory to the second DMA, the first DMA writes the data to buffer X of the transfer memory, while the second DMA reads from buffer Y. Then, the second DMA reads the data placed in buffer X, while the first DMA writes new data to buffer Y. After that, the second DMA read the new data placed in buffer Y, while the first DMA writes to buffer X, and so on. One problem with this method is that it is difficult for a memory control unit (MCU) to modify a buffer because there are no isolated buffers to modify.
While these approaches have provided improvements over prior approaches, the challenges in the field of data processing systems have continued to increase with demands for more and better techniques having greater speed and efficiency. Therefore, a need has arisen for a new method and system for data transfer.
In accordance with the present invention, a method and system for data transfer are provided that substantially eliminate or reduce the disadvantages and problems associated with previously developed systems and methods.
According to one embodiment of the present invention, a system for data transfer is disclosed that comprises a transfer memory having one or more buffers. Accessing units comprising direct memory access units are coupled to the transfer memory and are operable to access the transfer memory. Pointers stored in the transfer memory direct the accessing units to the buffers such that no two accessing units are simultaneously accessing one buffer. More specifically, the pointers may also direct a memory control unit to a buffer that is not being accessed by an accessing unit.
According to one embodiment of the present invention, a method for data transfer is disclosed. First, a transfer memory comprising one or more buffers is provided. Second, pointers that indicate a next buffer are stored in the transfer memory. Finally, accessing units comprising direct memory access units and operable to access the transfer memory are directed to the next buffer indicated by the pointer, such that no two accessing units are simultaneously accessing one buffer. More specifically, a memory control unit may be directed to a next buffer that is not being accessed by an accessing unit.
A technical advantage of the present invention is that it creates an isolated buffer that a memory control unit may modify while the DMAs are also accessing the transfer memory. Another technical advantage of the present invention is that the pointers direct the DMAs to many buffers in the transfer memory, allowing a first DMA to use multiple buffers to store data destined for a second DMA. More buffer space in a queue allows for a greater difference in transfer rates across the queue. As a result, the present invention enables fast, efficient pipelining of packets without processor intervention.